CMOS image sensors are increasingly being used as relatively low cost imaging devices. A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells includes a photo-conversion device, such as e.g., a photogate, photoconductor, or photodiode having an associated charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a sensing node, and a transistor for resetting the sensing node to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the sensing node and an access transistor, for controlling the readout of the cell contents from the source follower transistor.
In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the sensing node; (4) resetting the sensing node to a known state; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the sensing node.
CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,140,630, 6,177,333, 6,204,524, 6,310,366, 6,326,652, and 6,333,205, assigned to Micron Technology, Inc., the contents of which are incorporated herein by reference.
A typical four transistor (4T) CMOS imager pixel 150 is shown in FIG. 1A. The pixel 150 includes a photo-conversion device 100, which may be implemented as a pinned photodiode, transfer transistor 110, floating diffusion region FD, reset transistor 120, source follower transistor 130 and row select transistor 180. The photo-conversion device 100 is connected to the floating diffusion region FD by the transfer transistor 110 when the transfer transistor 110 is activated by a transfer gate control signal TX.
The reset transistor 120 is connected between the floating diffusion region FD and a pixel supply voltage Vpix. A reset control signal RST is used to activate the reset transistor 120, which resets the floating diffusion region FD to the pixel supply voltage Vpix level as is known in the art.
The source follower transistor 130 has its gate connected to the floating diffusion region FD and is connected between an array supply voltage Vaa and the row select transistor 180. The source follower transistor 130 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal PIX OUT. The row select transistor is controllable by a row select signal SEL for selectively connecting the source follower transistor 130 and its output voltage signal PIX OUT to a column line 190 of a pixel array.
FIG. 1B illustrates a simplified timing diagram for the readout and photo-charge integration operations for the pixel 150 illustrated in FIG. 1A. FIG. 1B illustrates a first readout period 181 in which previously stored photo-charges are readout of the pixel 150. During this first readout period 181, the reset control signal RST is pulsed to activate the reset transistor 120, which resets the floating diffusion region FD to the pixel supply voltage Vpix level. While the SEL signal is high, a sample and hold reset signal SHR is pulsed to store a reset signal Vrst (corresponding to the reset floating diffusion region FD) on a sample and hold capacitor of a sample and hold circuit (not shown in FIG. 1A or 1B). The transfer control signal TX is then activated to allow photo-charges from the photo-conversion device 100 to be transferred to the floating diffusion region FD. While the SEL signal remains high, a sample and hold pixel signal SHS is pulsed to store a pixel signal Vsig from the pixel 150 on another sample and hold capacitor of the sample and hold circuit.
During the integration period 191, the reset control signal RST, transfer control signal TX and sample and hold signals SHR, SHS are set to a ground potential GRND. It is during the integration period 191 that the photo-conversion device accumulates photo-charge based on the light incident on the photo-conversion device. After the integration period 191, a second readout period 171 begins. During the second readout period 171, the photo-charges accumulated in the integration period 191 are readout of the pixel 150 (as described above for period 181).
One common problem associated with conventional imager pixel cells, such as pixel cell 150, is dark current, that is, current generated as a photo-conversion device signal in the absence of light. As shown in the potential diagram of FIG. 1C, dark current 161 may be caused by many different factors, including: photosensor junction leakage, leakage along isolation edges, transistor sub-threshold leakage, drain induced barrier lower leakage, gate induced drain leakage, trap assisted tunneling, and pixel fabrication defects. One example of a defect is an interstitial vacancy state in the charge carrier-depletion region. This defect causes increased thermal generation of electron-hole pairs, which may be collected in the photo-conversion device 100 (FIG. 1A) and effectively lower overall image quality.
Accordingly, a pixel having a decreased dark current without negative blooming effects is desired. Also needed is a simple method of fabricating and operating such a pixel.